Product Summary
The sn74lvc1g86drlr is a single 2-input exclusive-OR gate. The sn74lvc1g86drlr is designed for 1.65-V to 5.5-V VCC operation. The sn74lvc1g86drlr performs the Boolean function Y = A Å B or Y = AB + AB in positive logic. A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Parametrics
sn74lvc1g86drlr absolute maximum ratings: (1)VDS Drain-Source Voltage: 20 V; (2)ID @ TA = 25°C Continuous Drain Current, VGS: 2.4A; (3)ID @ TA = 70°C Continuous Drain Current, VGS: 1.9A; (4)IDM Pulsed Drain Current: 19A; (5)PD @TA = 25°C Maximum Power Dissipation: 1.25 W; (6)PD @TA = 70°C Maximum Power Dissipation: 0.8 W; (7)Linear Derating Factor: 10 mW/°C; (8)VGS Gate-to-Source Voltage: ± 12 V; (9)VGSM Gate-to-Source Voltage Single Pulse tp<10μS: 16 V; (10)dv/dt Peak Diode Recovery dv/dt: 5.0V/ns; (11)TJ , TSTG Junction and Storage Temperature Range: -55 to + 150 °C.
Features
sn74lvc1g86drlr features: (1)Supports 5-V VCC Operation; (2)Inputs Accept Voltages to 5.5 V; (3)Max tpd of 4 ns at 3.3 V; (4)Low Power Consumption, 10-μA Max ICC; (5)±24-mA Output Drive at 3.3 V; (6)Ioff Supports Partial-Power-Down Mode.
Diagrams
Image | Part No | Mfg | Description | ![]() |
Pricing (USD) |
Quantity | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
![]() |
![]() SN74LVC1G86DRLR |
![]() Texas Instruments |
![]() Gates (AND / NAND / OR / NOR) Sngl2Inpt Exclusive |
![]() Data Sheet |
![]()
|
|
||||||||||||
![]() |
![]() SN74LVC1G86DRLRG4 |
![]() Texas Instruments |
![]() Gates (AND / NAND / OR / NOR) SNGL 2 Input Exclusive OR Gate |
![]() Data Sheet |
![]()
|
|