IR2113S

Product Summary

The IR2113S is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channel. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic. The IR2113S features a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600 volts.

Parametrics

IR2113S absolute maximum ratings: (1)High side floating supply voltage, VB: -0.3 to 625V; (2)High side floating supply offset voltage, VS: VB -25 to VB +0.3V; (3)High side floating output voltage, VHO: VS -0.3 to VB +0.3V; (4)Low side fixed supply voltage, VCC: -0.3 to 25V; (5)Low side output voltage, VLO: -0.3 to VCC +0.3V; (6)Logic supply voltage, VDD: -0.3 to VSS +25V; (7)Logic supply offset voltage, VSS: VCC -25 to VCC +0.3V; (8)Logic input voltage (HIN, LIN & SD), VIN: VSS -0.3 to VDD +0.3V; (9)Allowable offset supply voltage transient, dVs/dt: 50 V/ns; (10)Package power dissipation @ TA ≤ +25℃ (14 lead DIP), PD: 1.6W; (16 lead SOIC), PD: 1.25W; (11)Thermal resistance, junction to ambient (14 lead DIP), RTHJA: 75℃/W; (16 lead SOIC), RTHJA: 100℃/W; (12)Junction temperature, TJ: 150℃; (13)Storage temperature, TS: -55 to 150℃; (14)Lead temperature (soldering, 10 seconds), TL: 300℃.

Features

IR2113S features: (1)Floating channel designed for bootstrap operation Fully operational to +500V or +600V Tolerant to negative transient voltage dV/dt immune; (2)Gate drive supply range from 10 to 20V; (3)Undervoltage lockout for both channels; (4)3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground ±5V offset; (5)CMOS Schmitt-triggered inputs with pull-down; (6)Cycle by cycle edge-triggered shutdown logic; (7)Matched propagation delay for both channels; (8)Outputs in phase with inputs.

Diagrams