(China (Mainland))
Product Summary
The sn74lv164adr is an 8-bit parallel-out serial shift register designed for 2-V to 5.5-V VCC operation. The sn74lv164adr features AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input.
Parametrics
sn74lv164adr absolute maximum ratings: (1)Supply voltage range, VCC: -0.5 V to 7 V; (2)Input voltage range, VI: -0.5 V to 7 V; (3)Voltage range applied to any output in the high-impedance or power-off state, VO: -0.5 V to 7 V; (4)Output voltage range, VO: -0.5 V to VCC + 0.5 V; (5)Input clamp current, IIK (VI < 0): -20 mA; (6)Output clamp current, IOK (VO < 0): -50 mA; (7)Continuous output current, IO (VO = 0 to VCC): ±25 mA; (8)Continuous current through VCC or GND: ±50 mA; (9)Storage temperature range, Tstg: -65°C to 150°C.
Features
sn74lv164adr features: (1)2-V to 5.5-V VCC Operation; (2)Max tpd of 10.5 ns at 5 V; (3)Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°C; (4)Typical VOHV (Output VOH Undershoot)>2.3 V at VCC = 3.3 V, TA = 25°C; (5)Support Mixed-Mode Voltage Operation on All Ports; (6)Latch-Up Performance Exceeds 250 mA Per JESD 17; (7)ESD Protection Exceeds JESD 22.
Diagrams
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 SN74LV164ADR |
Texas Instruments |
Counter Shift Registers 8-Bit Parallel-Out Ser Shift Register |
Data Sheet |
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SN74LV164ADRE4 |
Texas Instruments |
Counter Shift Registers 8-Bit Parallel-Out Ser Shift Register |
Data Sheet |
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SN74LV164ADRG4 |
Texas Instruments |
Counter Shift Registers 8B Parallel Out Serial Shift Registr |
Data Sheet |
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