(China (Mainland))
Product Summary
The gal20v8c-7lj is a High Performance E2CMOS PLD Generic Array Logic at 5ns maximum propagation delay time. It combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture of gal20v8c-7lj provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20V8 are the PAL architectures listed in the table of the macrocell description section. The gal20v8c-7lj is capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.
Parametrics
gal20v8c-7lj absolute maximum ratings: (1)Supply voltage VCC: –0.5 to +7V; (2)Input voltage applied: –2.5 to VCC +1.0V; (3)Off-state output voltage applied: –2.5 to VCC +1.0V; (4)Storage Temperature: –65 to 150℃; (5)Ambient Temperature with Power Applied: –55 to 125℃.
Features
gal20v8c-7lj features: (1)high performance E2cmos technology: 5 ns Maximum Propagation Delay, Fmax = 166 MHz, 4 ns Maximum from Clock Input to Data Output, UltraMOS Advanced CMOS Technology; (2)50% to 75% reduction in power from bipola: 75mA Typ Icc on Low Power Device, 45mA Typ Icc on Quarter Power Device; (3)active pull-ups on all pins; (4)E2 cell technology: Reconfigurable Logic, Reprogrammable Cells, 100% Tested/100% Yields, High Speed Electrical Erasure (<100ms), 20 Year Data Retention; (5)eight output logic macrocells: Maximum Flexibility for Complex Logic Designs, Programmable Output Polarity, Also Emulates 24-pin PAL Devices with Full Function/Fuse Map/Parametric Compatibility.
Diagrams
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 GAL20V8C-7LJ |
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SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD |
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GAL20V8C-7LJN |
Lattice |
SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD |
Data Sheet |
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