(China (Mainland))
Product Summary
The MT48LC8M8A2TG-7E is a synchronous DRAM. The MT48LC8M8A2TG-7E is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. Each of the x8 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of the x16’s 16,777,216- bit banks is organized as 4,096 rows by 256 columns by 16 bits.
Parametrics
MT48LC8M8A2TG-7E absolute maximum ratings: (1)Voltage on VDD, VDDQ Supply Relative to VSS: -1V to +4.6V; (2)Voltage on Inputs, NC or I/O Pins Relative to VSS: -1V to +4.6V; (3)Operating Temperature, TA (commercial): 0°C to +70°C; (4)Operating Temperature, TA (extended; IT parts): -40°C to +85°C; (5)Storage Temperature (plastic): -55°C to +150°C; (6)Power Dissipatio : 1W.
Features
MT48LC8M8A2TG-7E features: (1)PC66-, PC100-, and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes; (7)Self Refresh Modes: standard and low power; (8)64ms, 4,096-cycle refresh; (9)LVTTL-compatible inputs and outputs; (10)Single +3.3V ±0.3V power supply.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||
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 MT48LC8M8A2TG-7E L:G |
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IC SDRAM 64MBIT 133MHZ 54TSOP |
Data Sheet |
Negotiable |
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MT48LC8M8A2TG-7E L:G TR |
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IC SDRAM 64MBIT 133MHZ 54TSOP |
Data Sheet |
Negotiable |
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MT48LC8M8A2TG-7E:G TR |
|
IC SDRAM 64MBIT 133MHZ 54TSOP |
Data Sheet |
Negotiable |
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