(China (Mainland))
Product Summary
The 74lvc138apwdh is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This multiple enable function allows easy parallel expansion of the 74lvc138apwdh to a 1-of-32 (5 lines to 32 lines) decoder with just four 74lvc138apwdh74lvc138apwdh ICs and one inverter. The 74lvc138apwdh can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
Parametrics
74lvc138apwdh absolute maximum ratings: (1)VCC DC supply voltage: –0.5 to +6.5 V; (2)IIK DC input diode current VI: 0 to 50 mA; (3)VI DC input voltage: –0.5 to +6.5 V; (4)IOK DC output diode current VOVCC or VO: 0 to 50 mA; (5)DC input voltage; output 3-State: –0.5 to 6.5V; (6)IO DC output source or sink current VO = 0 to VC: 50 mA; (7)IGND, ICC DC VCC or GND current: 100 mA; (8)Tstg Storage temperature range: –65 to +150 °C; (9)Power dissipation per package: 500 mW.
Features
74lvc138apwdh features: (1)Wide supply voltage range of 1.2 to 3.6 V; (2)In accordance with JEDEC standard no. 8-1A; (3)Inputs accept voltages up to 5.5 V; (4)CMOS lower power consumption; (5)Direct interface with TTL levels; (6)Demultiplexing capability; (7)Multiple input enable for easy expansion; (8)Ideal for memory chip select decoding; (9)Active LOW mutually exclusive outputs; (10)Output drive capability 50 transmission lines at 85°C.
Diagrams
