Product Summary
The 74LVC125ADB is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. The 74LVC125ADB consists of four non-inverting buffers/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high impedance OFF-state.
Parametrics
74LVC125ADB absolute maximum ratings: (1)DC supply voltage: -0.5 to +6.5 V; (2)DC input diode current: -50 mA; (3)DC input voltage Note 2: -0.5 to +6.5 V; (4)DC output diode current: ±50 mA; (5)DC output voltage; output HIGH or LOW state: -0.5 to VCC +0.5 V; (6)DC output voltage; output 3-State: -0.5 to 6.5 V; (7)DC output source or sink current: ±50 mA; (8)DC VCC or GND current: ±100 mA; (9)Storage temperature range: -65 to +150 °C; (10)Power dissipation per package - plastic mini-pack (SO)above +70°C derate linearly with 8 mW/K: 500 mW; (11)Power dissipation per package- plastic shrink mini-pack (SSOP and TSSOP)above +60°C derate linearly with 5.5 mW/K: 500 mW.
Features
74LVC125ADB features: (1)5-volt tolerant inputs/outputs, for interfacing with 5-volt logic; (2)Supply voltage range of 1.2V to 3.6V; (3)Complies with JEDEC standard no. 8-1A; (4)CMOS low power consumption; (5)Direct interface with TTL levels; (6)High impedance when VCC = 0V.
Diagrams

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![]() 74LVC125ADB,112 |
![]() NXP Semiconductors |
![]() Buffers & Line Drivers 3.3V QUAD 3-S BUS |
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![]() 74LVC125ADB,118 |
![]() NXP Semiconductors |
![]() Buffers & Line Drivers QUAD BUFF/DRVR 3ST 3.3V |
![]() Data Sheet |
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(China (Mainland))









