EP1S25F1020C6

EP1S25F1020C6, FPGA, 4.6 V, 40 mA, 300 MHz, BGA

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Price:: US $900.00~900.00 / piece [Get Latest Price]

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PartNumber:: EP1S25F1020C6

Brand:: Altera - Altera | Pack: | D/C:

Availability:: Supply Ability: 1/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2013-06-05

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Part Number:EP1S25F1020C6
US $900.00 - 900.00
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piece

Product Summary

The EP1S25F1020C6 FPGA is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. The EP1S25F1020C6 offer up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. The EP1S25F1020C6 supports various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs).

Parametrics

EP1S25F1020C6 absolute maximum ratings: (1)VCCINT Supply voltage With respect to ground: –0.5 to 2.4 V; (2)VCCIO: –0.5 to 4.6 V; (3)VI DC input voltage: –0.5 to 4.6 V; (4)IOUT DC output current, per pin: –25 to 40 mA; (5)TSTG Storage temperature No bias: –65 to 150 °C; (6)TJ Junction temperature BGA packages under bias: 135 °C.

Features

EP1S25F1020C6 features: (1)High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR)filters; (2)Up to 16 global clocks with 22 clocking resources per device region; (3)Up to 12 PLLs (four enhanced PLLs and eight fast PLLs)per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting; (4)Support for numerous single-ended and differential I/O standards; (5)High-speed differential I/O support on up to 116 channels with up; (6)to 80 channels optimized for 840 megabits per second (Mbps); (7)Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4; (8)Differential on-chip termination support for LVDS.