Product Summary
The 74hct299d is a high-speed Si-gate CMOS device. and The 74hct299d is pin compatible with low power Schottky TTL (LSTTL). The 74hct299d is specified in compliance with JEDEC standard no. 7A. The 74hct299d contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation of the 74hct299d is determined by the mode select inputs (S0 and S1), as shown in the mode select table.
Parametrics
74hct299d absolute maximum ratings: (1)tPHL/ tPLH, propagation delay: 20 ns; (2)fmax, maximum clock frequency: 50 MHz; (3)CI, input capacitance: 3.5 pF; (4)CI/O, input/output capacitance: 10 pF; (5)CPD, power dissipation capacitance per package notes 1 and 2: 120 pF.
Features
74hct299d features: (1)Multiplexed inputs/outputs provide improved bit density; (2)Four operating modes: shift left; (3)Operates with output enable or at high-impedance OFF-state (Z); (4)3-state outputs drive bus lines directly; (5)Can be cascaded for n-bits word length; (6)Output capability: bus driver (parallel I/Os), standard; (7)ICC category: MSI.
Diagrams
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![]() 74HCT299D,652 |
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![]() 74HCT299DB,112 |
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![]() 74HCT299D,653 |
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![]() Counter Shift Registers 8-BIT UNIVERSAL SHFT |
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![]() 74HCT299DB,118 |
![]() NXP Semiconductors |
![]() Counter Shift Registers 8-BIT UNIVERSAL SHFT |
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![]() |
![]() 74HCT299DB |
![]() NXP Semiconductors |
![]() Counter Shift Registers 8-BIT UNIVERSAL SHFT REG 3-S |
![]() Data Sheet |
![]() Negotiable |
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![]() 74HCT299DB-T |
![]() NXP Semiconductors |
![]() Counter Shift Registers 8-BIT UNIVERSAL SHFT REG 3-S |
![]() Data Sheet |
![]() Negotiable |
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![]() 74HCT299D-T |
![]() NXP Semiconductors |
![]() Counter Shift Registers 8-BIT UNIVERSAL SHFT REG 3-S |
![]() Data Sheet |
![]() Negotiable |
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