Product Summary
The sn74hc166dr is a parallel-in or serial-in, serial-out register. The sn74hc166dr features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The sn74hc166dr is established by the shift/load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input.
Parametrics
sn74hc166dr absolute maximum ratings: (1)Supply voltage range, VCC: -0.5 V to 7 V; (2)Input clamp current, IIK (VI < 0 or VI > VCC): ±20 mA; (3)Output clamp current, IOK (VO < 0 or VO > VCC): ±20 mA; (4)Continuous output current, IO (VO = 0 to VCC): ±25 mA; (5)Continuous current through VCC or GND: ±50 mA; (6)Storage temperature range, Tstg: -65°C to 150°C.
Features
sn74hc166dr features: (1)Wide Operating Voltage Range of 2 V to 6 V; (2)Outputs Can Drive Up To 10 LSTTL Loads; (3)Low Power Consumption, 80-μA Max ICC; (4)Typical tpd = 13 ns; (5)±4-mA Output Drive at 5 V; (6)Low Input Current of 1 μA Max; (7)Synchronous Load; (8)Direct Overriding Clear; (9)Parallel-to-Serial Conversion.
Diagrams
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![]() SN74HC166DR |
![]() Texas Instruments |
![]() Counter Shift Registers 8bit Parl Load Shift |
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![]() SN74HC166DRE4 |
![]() Texas Instruments |
![]() Counter Shift Registers 8-Bit Parallel-Load Shift Register |
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![]() SN74HC166DRG4 |
![]() Texas Instruments |
![]() Counter Shift Registers 8B Parallel Load Shift Registers |
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