SN74LVC573APWR

SN74LVC573APWR, octal transparent D-type latch, 6.5 V, 100 mA, TSSOP

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Price:: US $0.50~0.50 / piece [Get Latest Price]

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PartNumber:: SN74LVC573APWR

Brand:: Texas Instruments - TI | Pack: TSSOP | D/C: 07+

Availability:: Supply Ability: 4/Day Can Ship Immediately
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Products Upload time: 2013-06-27

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Part Number:SN74LVC573APWR
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Product Summary

The SN74LVC573APWR octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC573APWR octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC573APWR features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.

Parametrics

SN74LVC573APWR absolute maximum ratings: (1)VCC Supply voltage: –0.5 to 6.5 V; (2)VI Input voltage range: –0.5 to 6.5 V; (3)VO Voltage range applied to any output in the high-impedance or power-off state: –0.5 to 6.5 V; (4)VO Voltage range applied to any output in the high or low state: –0.5 to VCC + 0.5 V; (5)IIK Input clamp current VI < 0: –50 mA; (6)IOK Output clamp current VO < 0: –50 mA; (7)I°Continuous output current: ±50 mA; (8)Continuous current through VCC or GND: ±100 mA; (9)Tstg Storage temperature range: –65 to 150 °C.

Features

SN74LVC573APWR features: (1)Operate From 1.65 V to 3.6 V; (2)Ioff Supports Partial-Power-Down Mode; (3)Inputs Accept Voltages to 5.5 V Operation; (4)Max tpd of 6.9 ns at 3.3 V; (5)Latch-Up Performance Exceeds 250 mA Per; (6)Typical V JESD 17 OLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°C; (7)ESD Protection Exceeds JESD 22.