(China (Mainland))
Product Summary
The EPM9320RI208-2 is a in-system-programmable, high-density, highperformance EPLD which is based on the third-generation MAX architecture of Altera. Fabricated on an advanced CMOS technology, the EPM9320RI208-2 provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.
Parametrics
EPM9320RI208-2 absolute maximum ratings: (1)On the condition of with respect to ground, VCC Supply voltage: -2.0V to 7.0V; (2)On the condition of with respect to ground, VI DC input voltage -2.0V to 7.0V; (3)On the condition of with respect to ground, VCCISP Supply voltage during in-system programming: -2.0V to 7.0V; (4)IOUT DC output current, per pin: -25mA to 25mA; (5)On the condition of No bias, TSTG Storage temperature: -65℃ to 150℃; (6)On the condition of Under bias, TAMB Ambient temperature: -65℃ to 135℃; (7)On the conditions of Ceramic packages, under bias, TJ Junction temperature: 150℃; On the conditions of PQFP and RQFP packages, under bias: 135℃.
Features
EPM9320RI208-2 features: (1)High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX) architecture; (2)5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface; (3)Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (4)High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1); (5)10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz.
Diagrams
