Product Summary
The CD74HC73M is a K flip-flop. The CD74HC73M utilizes silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. The CD74HC73M exhibit the low power consumption of standard CMOS integrated circuit, together with the ability to.The CD74HC73M 10 LSTTL load.The CD74HC73M logic family is functionally as well as pin compatible with the standard 74LS logic family.
Parametrics
CD74HC73M absolute maximum ratings:(1)DC Supply Voltage, VCC : -0.5V to 7V; (2)DC Input Diode Current, I IK For VI < -0.5V or VI > VCC + 0.5V: 20mA; (3)DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V: 25mA; (4)DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V : 20mA; (5)DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V : 25mA; (6)DC VCC or Ground Current, ICC : 50m.
Features
CD74HC73M features:(1)Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times; (2)Asynchronous Reset; (3)Complementary Outputs; (4)Buffered Inputs; (5)Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25 o C; (6)Fanout (Over Temperature Range.; (7)4.5V to 5.5V Operation; (8)Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min).
Diagrams

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![]() CD74HC73M |
![]() Texas Instruments |
![]() Flip Flops Hi-Spd CMOS Dual Neg J-K Flip-Flop |
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![]() CD74HC73M96 |
![]() Texas Instruments |
![]() Flip Flops Dual |
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![]() CD74HC73M96G4 |
![]() Texas Instruments |
![]() Flip Flops Hi Spd CMOS Log Dual Neg-Edge-Trggrd J-K |
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![]() CD74HC73ME4 |
![]() Texas Instruments |
![]() Flip Flops Hi-Spd CMOS Dual Neg J-K Flip-Flop |
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![]() CD74HC73MG4 |
![]() Texas Instruments |
![]() Flip Flops Hi Spd CMOS Log Dual Neg-Edge-Trggrd J-K |
![]() Data Sheet |
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![]() CD74HC73M96E4 |
![]() Texas Instruments |
![]() Flip Flops Hi-Spd CMOS Dual Neg J-K Flip-Flop |
![]() Data Sheet |
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![]() CD74HC73MTG4 |
![]() Texas Instruments |
![]() Flip Flops Hi Spd CMOS Log Dual Neg-Edge-Trggrd J-K |
![]() Data Sheet |
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![]() |
![]() CD74HC73MTE4 |
![]() Texas Instruments |
![]() Flip Flops Hi-Spd CMOS Dual Neg J-K Flip-Flop |
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