Product Summary
The 74LVC2G74DC is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. The 74LVC2G74DC is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when the 74LVC2G74DC is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times.
Parametrics
74LVC2G74DC absolute maximum ratings: (1)VCC, supply voltage: -0.5 to +6.5 V; (2)IIK, input clamping current VI < 0 V: -50 mA; (3)VI, input voltage [1]: -0.5 to +6.5 V; (4)IOK, output clamping current VO > VCC or VO < 0 V: ±50 mA; (5)VO, output voltage active mode [1] [2]: -0.5 to VCC + 0.5 V; Power-down mode [1] [2]: -0.5 to +6.5 V; (6)IO, output current VO = 0 V to VCC: ±50 mA; (7)ICC, quiescent supply current: ±100 mA; (8)IGND, ground current - ±100 mA; (9)Tstg, storage temperature: -65 to +150 °C; (10)Ptot, total power dissipation Tamb = -40 °C to +125 °C: 250 mW.
Features
74LVC2G74DC features: (1)Wide supply voltage range from 1.65 V to 5.5 V; (2)5 V tolerant inputs for interfacing with 5 V logic; (3)High noise immunity; (4)Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V); JESD8-5 (2.3 V to 2.7 V); JESD8-B/JESD36 (2.7 V to 3.6 V); (5)±24 mA output drive (VCC = 3.0 V); (6)ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V; MM EIA/JESD22-A115-A exceeds 200 V; (7)CMOS low power consumption; (8)Latch-up performance exceeds 250 mA; (9)Direct interface with TTL levels; (10)Inputs accept voltages up to 5 V; (11)Multiple package options; (12)Specified from -40 °C to +85 °C and -40 °C to +125 °C.
Diagrams
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![]() 74LVC2G74DC,125 |
![]() NXP Semiconductors |
![]() Flip Flops BILATERAL SWITCH |
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![]() 74LVC2G74DC-G |
![]() NXP Semiconductors |
![]() Flip Flops BILATERAL SWITCH |
![]() Data Sheet |
![]() Negotiable |
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