Product Summary
The SN74LVC1G86DRLRG4 is a single 2-input exclusive-OR gate. It is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G86DRLRG4 performs the Boolean function Y = A Å B or Y = AB + AB in positive logic. A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. The SN74LVC1G86DRLRG4 is fully specified for partial-power-down applications using IOFF. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when the SN74LVC1G86DRLRG4 is powered down.
Parametrics
SN74LVC1G86DRLRG4 absolute maximum ratings: (1)Supply voltage range: –0.5 to 6.5 V; (2)Input voltage range(2): –0.5 to 6.5 V; (3)Voltage range applied to any output in the high-impedance or power-off state(2): –0.5 to 6.5 V; (4)Voltage range applied to any output in the high or low state(2)(3): –0.5 to VCC + 0.5 V; (5)IInput clamp current, VI < 0: –50 mA; (6)Output clamp current, VO < 0: –50 mA; (7)Continuous output current: ±50 mA; (8)Continuous current through VCC or GND: ±100 mA; (9)Package thermal impedance(4), DBV package: 206 °C/W; DCK package: 252 °C/W; YZP package: 132 °C/W; (10)Storage temperature range: –65 to 150 °C.
Features
SN74LVC1G86DRLRG4 features: (1)Available in the Texas Instruments NanoFree package; (2)Latch-Up performance exceeds 100 mA per JESD 78, class II; (3)Supports 5-V VCC operation; (4)Inputs accept voltages to 5.5 V; (5)ESD protection exceeds JESD 22: 2000-V human-body model (A114-A); 200-V machine model (A115-A); 1000-V charged-device model (C101); (6)IOFF supports partial-power-down mode operation; (7)Max tpd of 4 ns at 3.3 V; (8)Low power consumption, 10-μA max ICC; (9)±24-mA output drive at 3.3 V.
Diagrams
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