Product Summary
The 74HC377D is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC377D specified in compliance with JEDEC standard no. 7A. The 74HC377D have eight edge-triggered, D-type flip-flops with individual D input and Q output. A common clock (CP) input loads all flip-flop simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
Parametrics
74HC377D absolute maximum ratings: (1)Propagation delay CP to Qn CL = 15 pF; VCC = 5 V: 13 ns; (2)Maximum clock frequency: 77 MHz; (3)Input capacitance: 3.5 pF; (4)Power dissipation capacitance per flip-flop notes 1 and 2: 20 pF.
Features
74HC377D features: (1)Ideal for addressable register applications; (2)Data enable for address and data synchronization applications; (3)Eight positive-edge triggered D-type flip-flops; (4)See “273” for master reset version; (5)See “373” for transparent latch version; (6)See “374” for 3-state version; (7)Output capability: standard; (8)ICC category: MSI.
Diagrams
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![]() 74HC377DB,118 |
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![]() 74HC377DB |
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![]() 74HC377DB-T |
![]() NXP Semiconductors |
![]() Flip Flops OCTAL D-TYPE W/ENABL |
![]() Data Sheet |
![]() Negotiable |
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